1. Technical Field
The present invention relates to receiving and decoding serial digital data, and particularly to a high resolution, high speed, digital phase lock loop circuit that decodes Manchester encoded data into NRZ data and a clock signal.
2. Description of the Prior Art
Many kinds of information can be encoded and represented by binary numbers. A binary number has a predetermined length or number of digits, for example eight, and each digit has one of two possible values. A binary number may be expressed electronically by using high and low voltage signals known as no return to zero ("NRZ") bit signals, as shown, for example, in FIG. 1(a). These signals may be communicated from a transmitter to a receiver. It is commonly desirable to perform such communications through a single wire or equivalent path. This is done by transmitting the bits of one binary number (byte) serially, followed by the bits of the next byte, and so on.
For successful error free communication, the receiver must be able to distinguish individual bits. For example, two successive low voltage signals must not be mistaken for a single low signal. In general, serial transmitters use a precision clock to transmit data bits at a specified rate, and the receiver uses a matched clock to predict where to look for the boundaries of received data bits. As the transmission proceeds, however, the receiver clock will inevitably "drift" relative to the timing of the transmitter clock, impairing the receiver's tolerance of phase jitter and noise in the received signal.
One prior art solution to the problem of drift is to provide the transmitter clock signals to the receiver so that the two clocks may be resynchronized. One conventional technique for doing this is known as "Manchester" encoding of the data bits. According to that technique, the transmitter uses an exclusive OR (XOR) gate to combine the NRZ data bit signals to be communicated (FIG. 1a) with transmitter clock signals (FIG. 1b) which oscillate at twice the data bit transmission frequency. This produces a Manchester encoded data bit stream (FIG. 1c) in which the first half of each bit is the inverse value of the original NRZ data bit value, and the last half is the same value as the NRZ data bit. Any steps at boundaries of the original NRZ data bits are eliminated. However, more importantly, halfway between the boundaries of every Manchester data bit there is a step corresponding to a transmitter clock signal. A "preamble" of alternating NRZ 1's and 0's which are Manchester encoded without steps at bit boundaries, (FIG. 1c) is transmitted to enable the receiver to synchronize with and lock onto the transmitter clock signal. The receiver is thus able to distinguish individually received data bits, and to synchronize its internal processes to those of the transmitter without the need for a separately transmitted clock signal.
The receiver decodes the Manchester data to recover NRZ data by sampling each received data bit at several points. The receiver clock must be matched within 25% of the transmitter clock to sample for the transmitter clock within 1/4 bit of the transmitted clock edges, or samples will be taken on the wrong side of the mid-bit steps or outside the bit boundaries. With a 10 MHz clock signal, as typically used on Ethernet.RTM. local area networks, bits are each 100 nanoseconds (nsec) in duration, so the combined transmitter and receiver tolerance must be .+-.25 nsec (25% of 100 nsec) to assure accurate decoding. Because bit boundary deviations of 22 nsec are not unusual, the receiver must predict the transmitter clock to within .+-.3 nsec, and preferably to within .+-.2 nsec.
A conventional Phase Lock Loop (PLL) receiver circuit maintains its synchronization by comparing and adjusting its clock to received clock edges. High speed PLL receivers usually use analog circuitry. In an analog PLL, the received and receiver clock signals are supplied to a comparator which produces a constant voltage output pulse for the duration of the phase difference of the clock signals. The output pulse is integrated to produce a voltage, which is applied to a voltage controlled oscillator (VCO), to produce a phaselocked receiver clock signal. Analog PLL's have the potential for infinite resolution, but require external precision resistors and capacitors. Furthermore, analog circuits are susceptible to signal noise, which limits their resolution in practical implementations.
Digital PLL circuits do not require external precision components. However, the resolution of a digital PLL circuit is limited to its "effective" sampling interval, the minimum interval at which samples may be taken. In a PLL circuit a high speed clock signal increments a counter to a preselected number, and the counter supplies a sample clock pulse to a comparator for comparison with the received clock signals. Conventionally, if the sample clock signals lead, a pulse is dropped from the pulse stream supplied to a counter input terminal, to delay the count. If the sample clock signals lag, an extra pulse is inserted into the counter input stream.
This method of operation is undesirable because of the speed with which pulses must be added or subtracted. For example, for a digital PLL to operate by the conventional method within a 2 nsec margin of error desirable for receiving data at 10 MHz, samples would have to be taken at least once per 2 nsec, or at a 500 MHz rate. To insert an extra pulse into the counter input stream, the driver clock would have to operate at twice the sampling rate, 1 GHz, which is a 1 nsec pulse period. The pulses must be less than half of the period, say 0.4 nsec, with rise and fall times of 0.05 nsec each. Because the fastest satisfactory clock signal that can be generated by present technology is about 250 MHz, digital PLL decoding of a 10 MHz signal by conventional techniques cannot be achieved with the needed resolution. There is, therefore, a need for a digital PLL technique to provide an effective sampling interval shorter tha the driver clock period.